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» A Reduced Complexity Algorithm for Minimizing N-Detect Tests
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ICCAD
2006
IEEE
127views Hardware» more  ICCAD 2006»
14 years 5 months ago
Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
Murari Mani, Ashish Kumar Singh, Michael Orshansky
DATE
2006
IEEE
98views Hardware» more  DATE 2006»
14 years 2 months ago
Power-constrained test scheduling for multi-clock domain SoCs
This paper presents a wrapper and test access mechanism design for multi-clock domain SoCs that consists of cores with different clock frequencies during test. We also propose a t...
Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara
CDC
2008
IEEE
114views Control Systems» more  CDC 2008»
13 years 10 months ago
Dynamic test selection for reconfigurable diagnosis
Abstract-- Detecting and isolating multiple faults is a computationally intense task which typically consists of computing a set of tests, and then computing the diagnoses based on...
Mattias Krysander, Fredrik Heintz, Jacob Roll, Eri...
DAC
1996
ACM
14 years 17 days ago
Test Point Insertion: Scan Paths through Combinational Logic
We propose a low-overhead scan design methodology which employs a new test point insertion technique to establish scan paths through the functional logic. The technique re-uses th...
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-T...
HOTSWUP
2009
ACM
14 years 9 days ago
Efficient Systematic Testing for Dynamically Updatable Software
Recent years have seen significant advances in dynamic software updating (DSU) systems, which allow programs to be patched on the fly. However, a significant challenge remains: Ho...
Christopher M. Hayden, Eric A. Hardisty, Michael W...