515 search results - page 23 / 103 » A Reduced Complexity Algorithm for Minimizing N-Detect Tests |
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
Static Linked Faults are considered an interesting class of memory faults. Their capability of influencing the behavior of other faults causes the hiding of the fault effect and m...
DAC
2007
ACM
14 years 9 months ago
2007
ACM
The test time for core-external interconnect shorts/opens is typically much less than that for core-internal logic. Therefore, prior work on test infrastructure design for core-ba...
GLVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
DATE
1999
IEEE
14 years 23 days ago
1999
IEEE
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
CORR
2010
Springer
13 years 8 months ago
2010
Springer
-- Electing leader is a vital issue not only in distributed computing but also in communication network [1, 2, 3, 4, 5], centralized mutual exclusion algorithm [6, 7], centralized ...