154 search results - page 10 / 31 » A Register Allocation Technique Using Register Existence Gra... |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—In modern sub-micron design, achieving low-skew clock distributions is facing challenges for high-performance circuits. Symmetric global clock distribution and clock tree synthe...
EUROMICRO
1999
IEEE
13 years 11 months ago
1999
IEEE
This paper describes the DELFT-JAVA processor and the mechanisms required to dynamically translate JVM instructions into DELFT-JAVA instructions. Using a form of hardware register...
ICS
1995
Tsinghua U.
13 years 11 months ago
1995
Tsinghua U.
Modulo scheduling is an e cient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirement...
PPOPP
1990
ACM
13 years 11 months ago
1990
ACM
Abstract - A multiprocessor system capable of exploiting fine-grained parallelism must support efficient synchronization and data passing mechanisms. This paper demonstrates the us...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
Code optimization and high level synthesis can be posed as constraint satisfaction and optimization problems, such as graph coloring used in register allocation. Graph coloring is...