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CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and...
DAC
1996
ACM
13 years 11 months ago
1996
ACM
In this paper, we describe a technique for power reduction in sequential circuits. Existing signals in the circuit are used to selectively disable some of the registers so that a ...
CF
2008
ACM
13 years 9 months ago
2008
ACM
We develop architectural techniques for mitigating the impact of process variability. Our techniques hide the performance effects of slow components--including registers, function...
MICCAI
2001
Springer
13 years 12 months ago
2001
Springer
Abstract. This paper describes a new segmentation technique for multidimensional dynamic data. One example of such data is a perfusion sequence where a number of 3D MRI volumes sho...
LCPC
2009
Springer
14 years 1 days ago
2009
Springer
This paper improves our previous research effort [1] by providing an efficient method for kernel loop unrolling minimisation in the case of already scheduled loops, where circular...