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» A Reliability-Aware LDPC Code Decoding Algorithm
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ISCAS
2011
IEEE
288views Hardware» more  ISCAS 2011»
12 years 11 months ago
Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes
—We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered de...
Yang Sun, Guohui Wang, Joseph R. Cavallaro
ICC
2007
IEEE
147views Communications» more  ICC 2007»
14 years 1 months ago
VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax
— We present a new multi-rate architecture for decoding irregular LDPC codes in IEEE 802.16e WiMax standard. The proposed architecture utilizes the value–reuse property of offs...
Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary, Moha...
ICC
2007
IEEE
14 years 1 months ago
Low-Complexity, Low-Memory EMS Algorithm for Non-Binary LDPC Codes
— In this paper, we propose a new implementation of the EMS decoder for non binary LDPC codes presented in [7]. A particularity of the new algorithm is that it takes into account...
Adrian Voicila, David Declercq, François Ve...
VLSISP
2010
140views more  VLSISP 2010»
13 years 6 months ago
A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders
A Split decoding algorithm is proposed which divides each row of the parity check matrix into two or multiple nearly-independent simplified partitions. The proposed method signific...
Tinoosh Mohsenin, Bevan M. Baas
VLSID
2006
IEEE
158views VLSI» more  VLSID 2006»
14 years 1 months ago
Programmable LDPC Decoder Based on the Bubble-Sort Algorithm
Low density parity check (LDPC) codes are one of the most powerful error correcting codes known. Recent research have pointed out their potential for a low cost, low latency hardw...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra