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» A Reliability-Aware LDPC Code Decoding Algorithm
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SIPS
2006
IEEE
14 years 1 months ago
Partly Parallel Overlapped Sum-Product Decoder Architectures for Quasi-Cyclic LDPC Codes
Abstract— In this paper, we propose partly parallel architectures based on optimal overlapped sum-product (OSP) decoding. To ensure high throughput and hardware utilization effi...
Ning Chen, Yongmei Dai, Zhiyuan Yan
ISCAS
2005
IEEE
126views Hardware» more  ISCAS 2005»
14 years 1 months ago
Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation
— The fully parallel LDPC decoding architecture can achieve high decoding throughput, but it suffers from large hardware complexity caused by a large set of processing units and ...
In-Cheol Park, Se-Hyeon Kang
CORR
2006
Springer
141views Education» more  CORR 2006»
13 years 7 months ago
Iterative Decoding Performance Bounds for LDPC Codes on Noisy Channels
The asymptotic iterative decoding performances of low-density parity-check (LDPC) codes using min-sum (MS) and sum-product (SP) decoding algorithms on memoryless binary-input outp...
Chun-Hao Hsu, Achilleas Anastasopoulos
ISCAS
2007
IEEE
141views Hardware» more  ISCAS 2007»
14 years 1 months ago
Towards a GBit/s Programmable Decoder for LDPC Convolutional Codes
Abstract— We analyze the decoding algorithm for regular timeinvariant LDPC convolutional codes as a 3D signal processing scheme and derive several parallelization concepts, which...
Emil Matús, Marcos B. S. Tavares, Marcel Bi...
ICC
2007
IEEE
145views Communications» more  ICC 2007»
14 years 1 months ago
Lowering Error Floor of LDPC Codes Using a Joint Row-Column Decoding Algorithm
Low-density parity-check codes using the beliefpropagation decoding algorithm tend to exhibit a high error floor in the bit error rate curves, when some problematic graphical stru...
Zhiyong He, Sébastien Roy 0002, Paul Fortie...