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» A Scalable FPGA-based Multiprocessor
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DATE
2006
IEEE
100views Hardware» more  DATE 2006»
14 years 2 months ago
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
NoC architectures can be adopted to support general communications among multiple IPs over multi-processor Systems on Chip (SoCs). In this work we illustrate the modeling and simu...
Luciano Bononi, Nicola Concer
ICDM
2006
IEEE
147views Data Mining» more  ICDM 2006»
14 years 2 months ago
Adaptive Parallel Graph Mining for CMP Architectures
Mining graph data is an increasingly popular challenge, which has practical applications in many areas, including molecular substructure discovery, web link analysis, fraud detect...
Gregory Buehrer, Srinivasan Parthasarathy, Yen-Kua...
ISCA
2006
IEEE
151views Hardware» more  ISCA 2006»
14 years 2 months ago
The BlackWidow High-Radix Clos Network
This paper describes the radix-64 folded-Clos network of the Cray BlackWidow scalable vector multiprocessor. We describe the BlackWidow network which scales to 32K processors with...
Steve Scott, Dennis Abts, John Kim, William J. Dal...
CAMP
2005
IEEE
14 years 2 months ago
Bio-Inspired Computing Architectures: The Embryonics Approach
Abstract— The promise of next-generation computer technologies, such as nano-electronics, implies a number of serious alterations to the design flow of digital circuits. One of ...
Gianluca Tempesti, Daniel Mange, André Stau...
CODES
2002
IEEE
14 years 1 months ago
Communication speed selection for embedded systems with networked voltage-scalable processors
High-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modern embedded systems, thanks to their size advantage and power ef...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh