30 search results - page 3 / 6 » A Scalable Instruction Queue Design Using Dependence Chains |
SBACPAD
2005
IEEE
14 years 28 days ago
2005
IEEE
Complexity is one of the most important problems facing microarchitects. It is exacerbated by the application of optimizations, by scaling to higher issue widths and, in general, ...
HPCA
2003
IEEE
14 years 7 months ago
2003
IEEE
To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundament...
HPCA
2006
IEEE
14 years 7 months ago
2006
IEEE
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...
MICRO
2005
IEEE
14 years 28 days ago
2005
IEEE
Conventional processors use a fully-associative store queue (SQ) to implement store-load forwarding. Associative search latency does not scale well to capacities and bandwidths re...
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
The negative performance impact of branch mis-predictions can be reduced by exploiting control independence (CI). When a branch mis-predicts, the wrong-path instructions up to the...