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» A Scalable Instruction Queue Design Using Dependence Chains
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MICRO
2005
IEEE
114views Hardware» more  MICRO 2005»
14 years 28 days ago
Address-Indexed Memory Disambiguation and Store-to-Load Forwarding
This paper describes a scalable, low-complexity alternative to the conventional load/store queue (LSQ) for superscalar processors that execute load and store instructions speculat...
Sam S. Stone, Kevin M. Woley, Matthew I. Frank
MICRO
1997
IEEE
86views Hardware» more  MICRO 1997»
13 years 11 months ago
Streamlining Inter-Operation Memory Communication via Data Dependence Prediction
We revisit memory hierarchy design viewing memory as an inter-operation communication agent. This perspective leads to the development of novel methods of performing inter-operati...
Andreas Moshovos, Gurindar S. Sohi
MICRO
2002
IEEE
143views Hardware» more  MICRO 2002»
14 years 8 days ago
Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor
Clustering is a common technique to overcome the wire delay problem incurred by the evolution of technology. Fully-distributed architectures, where the register file, the functio...
Enric Gibert, F. Jesús Sánchez, Anto...
ECRTS
2006
IEEE
14 years 1 months ago
The Dependency Management Framework: A Case Study of the ION CubeSat
Due to the complexity and requirements of modern realtime systems, multiple teams must often work concurrently and independently to develop the various components of the system. S...
Hui Ding, Leon Arber, Lui Sha, Marco Caccamo
HPCA
2008
IEEE
14 years 7 months ago
Fundamental performance constraints in horizontal fusion of in-order cores
A conceptually appealing approach to supporting a broad range of workloads is a system comprising many small cores that can be fused, on demand, into larger cores. We demonstrate ...
Pierre Salverda, Craig B. Zilles