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FPGA
2011
ACM
401views FPGA» more  FPGA 2011»
12 years 11 months ago
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
In this paper, we introduce a new open source high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. LegUp accepts a standard C pro...
Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zh...
ASPDAC
2005
ACM
133views Hardware» more  ASPDAC 2005»
13 years 9 months ago
A novel O(n) parallel banker's algorithm for System-on-a-Chip
This paper proposes a novel O(n) Parallel Banker’s Algorithm (PBA) with a best-case run-time of O(1), reduced from an ¢¤£¦¥¨§© run-time complexity of the original Ban...
Jaehwan John Lee, Vincent John Mooney III
LCTRTS
1998
Springer
14 years 3 days ago
Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques
Abstract. Previously published methods for estimation of the worstcase execution time on contemporary processors with complex pipelines and multi-level memory hierarchies result in...
Thomas Lundqvist, Per Stenström
CCECE
2006
IEEE
14 years 1 months ago
A Software Defined Radio Receiver Architecture for UWB Communications and Positioning
A software defined radio (SDR) receiver architecture is proposed in this paper for ultra-wideband (UWB) applications. Both UWB data communication and positioning functions are imp...
Yanyang Zhao, Ligen Wang, Jean-François Fri...
ISLPED
2004
ACM
123views Hardware» more  ISLPED 2004»
14 years 1 months ago
An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes
Increasing demand for larger high-performance applications requires developing more complex systems with hundreds of processing cores on a single chip. To allow dynamic voltage sc...
Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou