1234 search results - page 132 / 247 » A Scheduling and Pipelining Algorithm for Hardware Software ... |
LCTRTS
2010
Springer
14 years 2 months ago
2010
Springer
Coarse Grain Reconfigurable Architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and movi...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
In a behavioral synthesis system, a typical approach used to guide the scheduler is to impose hard constraints on the relative timing between operations considering performance, a...
ECBS
2007
IEEE
13 years 11 months ago
2007
IEEE
Due to the high cost of modeling, model-based techniques are yet to make their impact in the embedded systems industry, which still persist on maintaining code-oriented legacy sys...
DATE
1999
IEEE
14 years 5 days ago
1999
IEEE
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...
SIGMETRICS
1993
ACM
13 years 12 months ago
1993
ACM
Input/output subsystem performance is currently receiving considerable research attention. Signi cant e ort has been focused on reducing average I/O response times and increasing ...