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ISCA
2003
IEEE
169views Hardware» more  ISCA 2003»
14 years 26 days ago
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems
Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis t...
Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, ...
DATE
2004
IEEE
119views Hardware» more  DATE 2004»
13 years 11 months ago
Configuration-Sensitive Process Scheduling for FPGA-Based Computing Platforms
Reconfigurable computing has become an important part of research in software systems and computer architecture. While prior research on reconfigurable computing have addressed ar...
Guilin Chen, Mahmut T. Kandemir, Ugur Sezer
CISIS
2008
IEEE
14 years 2 months ago
Hardware Software Partitioning Problem in Embedded System Design Using Particle Swarm Optimization Algorithm
Hardware/software partitioning is a crucial problem in embedded system design. In this paper, we provide an alternative approach to solve this problem using Particle Swarm Optimiz...
Alakananda Bhattacharya, Amit Konar, Swagatam Das,...
DAC
1992
ACM
13 years 11 months ago
High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers
Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of ADAS which controls the hardware-softwa...
Ing-Jer Huang, Alvin M. Despain
HPCC
2007
Springer
14 years 1 months ago
Software Pipelining for Packet Filters
Packet filters play an essential role in traffic management and security management on the Internet. In order to create software-based packet filters that are fast enough to work...
Yoshiyuki Yamashita, Masato Tsuru