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ICCAD
2009
IEEE
179views Hardware» more  ICCAD 2009»
13 years 5 months ago
Automatic memory partitioning and scheduling for throughput and power optimization
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
Jason Cong, Wei Jiang, Bin Liu, Yi Zou
FPL
2008
Springer
120views Hardware» more  FPL 2008»
13 years 9 months ago
An FPGA-based implementation of the MINRES algorithm
Due to continuous improvements in the resources available on FPGAs, it is becoming increasingly possible to accelerate floating point algorithms. The solution of a system of linea...
David Boland, George A. Constantinides
ICCAD
2003
IEEE
325views Hardware» more  ICCAD 2003»
14 years 27 days ago
Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading
While performance, area, and power constraints have been the driving force in designing current communication-enabled embedded systems, post-fabrication and run-time adaptability ...
Brian Swahn, Soha Hassoun
EUROPAR
2009
Springer
14 years 6 days ago
A New Genetic Algorithm for Scheduling for Large Communication Delays
Abstract. In modern parallel and distributed systems, the time for exchanging data is usually larger than that for computing elementary operations. Consequently, these communicatio...
Johnatan E. Pecero, Denis Trystram, Albert Y. Zoma...
CODES
2006
IEEE
13 years 11 months ago
Increasing hardware efficiency with multifunction loop accelerators
To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...