1234 search results - page 29 / 247 » A Scheduling and Pipelining Algorithm for Hardware Software ... |
ISCA
2003
IEEE
14 years 27 days ago
2003
IEEE
To achieve high instruction throughput, instruction schedulers must be capable of producing high-quality schedules that maximize functional unit utilization while at the same time...
ICCAD
1998
IEEE
13 years 12 months ago
1998
IEEE
The performance of many modern computer and communication systems is dictated by latency of communication pipelines. At the same time, power consumption is often another limiting ...
EAAI
2006
13 years 7 months ago
2006
This paper presents a feasibility study of evolutionary scheduling for gas pipeline operations. The problem is complex because of several constraints that must be taken into consi...
JEC
2006
13 years 7 months ago
2006
Many applications commonly found in digital signal processing and image processing applications can be represented by data-flow graphs (DFGs). In our previous work, we proposed a ...
ICCD
1995
IEEE
13 years 11 months ago
1995
IEEE
Optimization of hardware resources for conditional data-flow graph behavior is particularly important when conditional behavior occurs in cyclic loops and maximization of through...