1234 search results - page 52 / 247 » A Scheduling and Pipelining Algorithm for Hardware Software ... |
RTSS
2006
IEEE
14 years 1 months ago
2006
IEEE
Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-pr...
CASES
2007
ACM
13 years 11 months ago
2007
ACM
This paper tackles the problem of providing correct information about program variable values in a software-pipelined loop through a non-transparent debugging approach. Since mode...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
CODES
2002
IEEE
14 years 20 days ago
2002
IEEE
In many embedded systems, existence of a data cache might influence the effectiveness of process scheduling policy significantly. Consequently, a scheduling policy that takes in...
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and...