1234 search results - page 52 / 247 » A Scheduling and Pipelining Algorithm for Hardware Software ... |
147
Voted
RTSS
2006
IEEE
15 years 8 months ago
2006
IEEE
Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-pr...
92
Voted
CASES
2007
ACM
15 years 6 months ago
2007
ACM
This paper tackles the problem of providing correct information about program variable values in a software-pipelined loop through a non-transparent debugging approach. Since mode...
143
Voted
DAC
2006
ACM
16 years 3 months ago
2006
ACM
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
144
Voted
CODES
2002
IEEE
15 years 7 months ago
2002
IEEE
In many embedded systems, existence of a data cache might influence the effectiveness of process scheduling policy significantly. Consequently, a scheduling policy that takes in...
114
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CODES
2004
IEEE
15 years 6 months ago
2004
IEEE
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and...