1234 search results - page 54 / 247 » A Scheduling and Pipelining Algorithm for Hardware Software ... |
ISLPED
2003
ACM
14 years 29 days ago
2003
ACM
We propose a novel power-aware task scheduling algorithm for DVS-enabled real-time multiprocessor systems. Unlike the existing algorithms, the proposed DVS algorithm can handle co...
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
- To date, most high-level synthesis systems do not automatically solve present design problems, such as those related to timing associated with the physical implementation of mult...
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
Abstract— Several network security and QoS applications require detecting multiple string matches in the packet payload by comparing it against predefined pattern set. This proc...
ARCS
2006
Springer
13 years 11 months ago
2006
Springer
The performance of the barrier operation can be crucial for many parallel codes. Especially distributed shared memory systems have to synchronize frequently to ensure the proper o...
LCTRTS
2010
Springer
13 years 5 months ago
2010
Springer
Concurrent Action-Oriented Specifications (CAOS) model the behavior of a synchronous hardware circuit as asynchronous guarded at an abstraction level higher than the Register Tran...