1234 search results - page 5 / 247 » A Scheduling and Pipelining Algorithm for Hardware Software ... |
120
Voted
ICPP
2002
IEEE
15 years 7 months ago
2002
IEEE
Code size expansion of software-pipelined loops is a critical problem for DSP systems with strict code size constraint. Some ad-hoc code size reduction techniques were used to try...
85
Voted
CODES
2005
IEEE
15 years 8 months ago
2005
IEEE
168
Voted
FPGA
2010
ACM
15 years 3 months ago
2010
ACM
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
116
Voted
GLVLSI
2005
IEEE
15 years 8 months ago
2005
IEEE
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
142
Voted
DAC
1997
ACM
15 years 7 months ago
1997
ACM
: Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power and cost goals. In t...