1234 search results - page 5 / 247 » A Scheduling and Pipelining Algorithm for Hardware Software ... |
ICPP
2002
IEEE
14 years 15 days ago
2002
IEEE
Code size expansion of software-pipelined loops is a critical problem for DSP systems with strict code size constraint. Some ad-hoc code size reduction techniques were used to try...
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
FPGA
2010
ACM
13 years 7 months ago
2010
ACM
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
: Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power and cost goals. In t...