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RSP
2006
IEEE
102views Control Systems» more  RSP 2006»
14 years 2 months ago
Rapid Resource-Constrained Hardware Performance Estimation
In a hardware-software co-design environment, an application is partitioned into modules. Each module is then mapped either to software or to hardware. The mapping process is driv...
Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrish...
IPPS
1998
IEEE
14 years 9 days ago
HOSMII: A Virtual Hardware Integrated with DRAM
WASMII, a virtual hardware system that executes data ow algorithms, is based on an MPLD, an extended FPGA with multiple sets of con guration SRAM. Although we have developed an emu...
Yuichiro Shibata, Hidenori Miyazaki, Xiao-ping Lin...
DATE
2009
IEEE
172views Hardware» more  DATE 2009»
14 years 2 months ago
On bounding response times under software transactional memory in distributed multiprocessor real-time systems
We consider multiprocessor distributed real-time systems where concurrency control is managed using software transactional memory (or STM). For such a system, we propose an algori...
Sherif Fadel Fahmy, Binoy Ravindran, E. Douglas Je...
DNA
2007
Springer
106views Bioinformatics» more  DNA 2007»
13 years 12 months ago
Hardware Acceleration for Thermodynamic Constrained DNA Code Generation
Reliable DNA computing requires a large pool of oligonucleotides that do not produce cross-hybridize. In this paper, we present a transformed algorithm to calculate the maximum wei...
Qinru Qiu, Prakash Mukre, Morgan Bishop, Daniel J....
ASPDAC
1995
ACM
103views Hardware» more  ASPDAC 1995»
13 years 11 months ago
A scheduling algorithm for multiport memory minimization in datapath synthesis
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
Hae-Dong Lee, Sun-Young Hwang