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» A Self-Reconfigurable Gate Array Architecture
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FPL
2009
Springer
113views Hardware» more  FPL 2009»
14 years 7 days ago
Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays
Spatially-tiled architectures, such as Coarse-Grained Reconfigurable Arrays (CGRAs), are powerful architectures for accelerating applications in the digital-signal processing, em...
Brian Van Essen, Aaron Wood, Allan Carroll, Stephe...
ISCAS
1995
IEEE
91views Hardware» more  ISCAS 1995»
13 years 11 months ago
An FPGA Based Reconfigurable Coprocessor Board Utilizing a Mathematics of Arrays
Abstract -- Work in progress at the University of Missouri-Rolla on hardware assists for high performance computing is presented. This research consists of a novel field programmab...
W. Eatherton, J. Kelly, T. Schiefelbein, H. Pottin...
IGARSS
2009
13 years 5 months ago
High Performance Computing for Hyperspectral Image Analysis: Perspective and State-of-the-art
The main purpose of this paper is to describe available (HPC)based implementations of remotely sensed hyperspectral image processing algorithms on multi-computer clusters, heterog...
Antonio Plaza, Qian Du, Yang-Lang Chang
ISLPED
2005
ACM
90views Hardware» more  ISLPED 2005»
14 years 1 months ago
Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices
This paper studies the impact on energy efficiency and thermal behavior of design style and clock-gating style in queue and array structures. These structures are major sources of...
Yingmin Li, Mark Hempstead, Patrick Mauro, David B...
CHES
2006
Springer
119views Cryptology» more  CHES 2006»
13 years 11 months ago
NanoCMOS-Molecular Realization of Rijndael
This paper describes the implementation of the Advanced Encryption Standard Algorithm, Rijndael, in a new nanoscale technology, called CMOL. This technology consists of an array of...
Massoud Masoumi, Farshid Raissi, Mahmoud Ahmadian