210 search results - page 26 / 42 » A Self-Reconfigurable Gate Array Architecture |
FCCM
2006
IEEE
14 years 1 months ago
2006
IEEE
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony’s Playstation 2 vector units offer scope for hardware acceleration of applications. Implementin...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— Low-density parity-check convolutional codes offer the same good error-correcting performance as low-density parity-check block codes while having the ability to encode and dec...
APCSAC
2000
IEEE
14 years 2 days ago
2000
IEEE
Hardware square-root units require large numbers of gates even for iterative implementations. In this paper, we present four low-cost high-performance fullypipelined n-select impl...
CORR
2008
Springer
13 years 7 months ago
2008
Springer
On modern architectures, the performance of 32-bit operations is often at least twice as fast as the performance of 64-bit operations. By using a combination of 32-bit and 64-bit ...
AHS
2006
IEEE
14 years 1 months ago
2006
IEEE
Traditional approaches to evolvable hardware (EHW), in which the field programmable gate array (FPGA) configuration is directly encoded, have not scaled well with increasing cir...