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» A Self-Reconfigurable Gate Array Architecture
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ICCAD
2003
IEEE
194views Hardware» more  ICCAD 2003»
14 years 4 months ago
On the Interaction Between Power-Aware FPGA CAD Algorithms
As Field-Programmable Gate Array (FPGA) power consumption continues to increase, lower power FPGA circuitry, architectures, and Computer-Aided Design (CAD) tools need to be develo...
Julien Lamoureux, Steven J. E. Wilton
CODES
2008
IEEE
14 years 2 months ago
Highly-cited ideas in system codesign and synthesis
We conducted a study of citations of papers published between 1996 and 2006 in the CODES and ISSS conferences, representing the hardware/software codesign and system synthesis com...
Frank Vahid, Tony Givargis
DAC
2003
ACM
14 years 27 days ago
Fast timing-driven partitioning-based placement for island style FPGAs
In this paper we propose a partitioning-based placement algorithm for FPGAs. The method incorporates simple, but effective heuristics that target delay minimization. The placement...
Pongstorn Maidee, Cristinel Ababei, Kia Bazargan
FCCM
2004
IEEE
163views VLSI» more  FCCM 2004»
13 years 11 months ago
Implementation Results of Bloom Filters for String Matching
Network Intrusion Detection and Prevention Systems (IDPS) use string matching to scan Internet packets for malicious content. Bloom filters offer a mechanism to search for a large...
Michael Attig, Sarang Dharmapurikar, John W. Lockw...
FPGA
2000
ACM
128views FPGA» more  FPGA 2000»
13 years 11 months ago
Factoring large numbers with programmable hardware
The fastest known algorithms for factoring large numbers share a core sieving technique. The sieving cores find numbers that are completely factored over a prime base set raised t...
Hea Joung Kim, William H. Mangione-Smith