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» A Self-Reconfigurable Gate Array Architecture
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DAC
1994
ACM
13 years 11 months ago
Optimum Functional Decomposition Using Encoding
In this paper, we revisit the classical problem of functional decomposition [1, 2] that arises so often in logic synthesis. One basic problem that has remained largely unaddressed...
Rajeev Murgai, Robert K. Brayton, Alberto L. Sangi...
JCP
2008
119views more  JCP 2008»
13 years 7 months ago
Performance Comparisons, Design, and Implementation of RC5 Symmetric Encryption Core using Reconfigurable Hardware
With the wireless communications coming to homes and offices, the need to have secure data transmission is of utmost importance. Today, it is important that information is sent con...
Omar S. Elkeelany, Adegoke Olabisi
DAC
2004
ACM
14 years 8 months ago
Dynamic FPGA routing for just-in-time FPGA compilation
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
FCCM
2002
IEEE
126views VLSI» more  FCCM 2002»
14 years 17 days ago
Hyperspectral Image Compression on Reconfigurable Platforms
NASA’s satellites currently do not make use of advanced image compression techniques during data transmission to earth because of limitations in the available platforms. With th...
Thomas W. Fry, Scott Hauck
FCCM
1998
IEEE
149views VLSI» more  FCCM 1998»
13 years 12 months ago
Configuration Compression for the Xilinx XC6200 FPGA
One of the major overheads in reconfigurable computing is the time it takes to reconfigure the devices in the system. This overhead limits the speedups possible in this exciting n...
Scott Hauck, Zhiyuan Li, Eric J. Schwabe