132 search results - page 23 / 27 » A Self-Tuning Configurable Cache |
ISPASS
2005
IEEE
14 years 28 days ago
2005
IEEE
Performance evaluation using only a subset of programs from a benchmark suite is commonplace in computer architecture research. This is especially true during early design space e...
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems...
MICRO
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our...
ICDE
2003
IEEE
14 years 8 months ago
2003
IEEE
The performance of streaming media servers has been limited due to the dual requirements of high throughput and low memory use. Although disk throughput has been enjoying a 40% an...
DAC
1998
ACM
14 years 8 months ago
1998
ACM
The growing class of portable systems, such as personal computing and communication devices, has resulted in a new set of system design requirements, mainly characterized by domin...