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» A Self-Tuning Configurable Cache

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CANPC
1999
Springer

122views Communications» more CANPC 1999»

Implementing Application-Specific Cache-Coherence Protocols in Configurable Hardware

13 years 11 months ago

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Streamlining communication is key to achieving good performance in shared-memory parallel programs. While full hardware support for cache coherence generally offers the best perfo...

David Brooks, Margaret Martonosi

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GECCO
2009
Springer

192views Optimization» more GECCO 2009»

Improving SMT performance: an application of genetic algorithms to configure resizable caches

13 years 4 months ago

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Simultaneous Multithreading (SMT) is a technology aimed at improving the throughput of the processor core by applying Instruction Level Parallelism (ILP) and Thread Level Parallel...

Josefa Díaz, José Ignacio Hidalgo, F...

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ISVLSI
2003
IEEE

101views VLSI» more ISVLSI 2003»

Energy Benefits of a Configurable Line Size Cache for Embedded Systems

13 years 12 months ago

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Previous work has shown that cache line sizes impact performance differently for different desktop programs – some programs work better with small line sizes, others with larger...

Chuanjun Zhang, Frank Vahid, Walid A. Najjar

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ASPDAC
2006
ACM

99views Hardware» more ASPDAC 2006»

Finding optimal L1 cache configuration for embedded systems

14 years 20 days ago