Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

26

ISCA
2003
IEEE

favoriteEmaildiscussreport

124views Hardware» more ISCA 2003»

A Highly-Configurable Cache Architecture for Embedded Systems

14 years 4 months ago

A Highly-Configurable Cache Architecture for Embedded Systems

Download www.cs.ucr.edu

Chuanjun Zhang, Frank Vahid, Walid A. Najjar

Real-time Traffic

Hardware | ISCA 2003 |

claim paper

Related Content

» Tuning of Loop Cache Architectures to Programs in Embedded System Design

» Improved indexing for cache miss reduction in embedded systems

» Towards TimePredictable Data Caches for ChipMultiprocessors

» Memory Exploration for Low Power Embedded Systems

» Performance and energy tradeoffs analysis of L2 onchip cache architectures for embedded MP...

» Eliminating interprocess cache interference through cache reconfigurability for realtime a...

» A nonuniform cache architecture for low power system design

» WCETcentric partial instruction cache locking

» Multiple sleep mode leakage control for cache peripheral circuits in embedded processors

Post Info
More Details (n/a)

Added	04 Jul 2010
Updated	04 Jul 2010
Type	Conference
Year	2003
Where	ISCA
Authors	Chuanjun Zhang, Frank Vahid, Walid A. Najjar

Comments (0)