Sciweavers
Explore
Publications
Books
Software
Tutorials
Presentations
Lectures Notes
Datasets
Labs
Conferences
Community
Upcoming
Conferences
Top Ranked Papers
Most Viewed Conferences
Conferences by Acronym
Conferences by Subject
Conferences by Year
Tools
Sci2ools
International Keyboard
Graphical Social Symbols
CSS3 Style Generator
OCR
Web Page to Image
Web Page to PDF
Merge PDF
Split PDF
Latex Equation Editor
Extract Images from PDF
Convert JPEG to PS
Convert Latex to Word
Convert Word to PDF
Image Converter
PDF Converter
Community
Sciweavers
About
Terms of Use
Privacy Policy
Cookies
Free Online Productivity Tools
i2Speak
i2Symbol
i2OCR
iTex2Img
iWeb2Print
iWeb2Shot
i2Type
iPdf2Split
iPdf2Merge
i2Bopomofo
i2Arabic
i2Style
i2Image
i2PDF
iLatex2Rtf
Sci2ools
22
click to vote
ISCA
2003
IEEE
favorite
Email
discuss
report
124
views
Hardware
»
more
ISCA 2003
»
A Highly-Configurable Cache Architecture for Embedded Systems
14 years 1 months ago
Download
www.cs.ucr.edu
Chuanjun Zhang, Frank Vahid, Walid A. Najjar
Real-time Traffic
Hardware
|
ISCA 2003
|
claim paper
Related Content
»
Tuning of Loop Cache Architectures to Programs in Embedded System Design
»
Improved indexing for cache miss reduction in embedded systems
»
Towards TimePredictable Data Caches for ChipMultiprocessors
»
Memory Exploration for Low Power Embedded Systems
»
Performance and energy tradeoffs analysis of L2 onchip cache architectures for embedded MP...
»
Eliminating interprocess cache interference through cache reconfigurability for realtime a...
»
A nonuniform cache architecture for low power system design
»
WCETcentric partial instruction cache locking
»
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors
more »
Post Info
More Details (n/a)
Added
04 Jul 2010
Updated
04 Jul 2010
Type
Conference
Year
2003
Where
ISCA
Authors
Chuanjun Zhang, Frank Vahid, Walid A. Najjar
Comments
(0)
Researcher Info
Hardware Study Group
Computer Vision