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» A Semantics for Multiprocessor Systems
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118
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DATE
2003
IEEE
180views Hardware» more  DATE 2003»
15 years 9 months ago
Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors
Software implementations of channel decoding algorithms are attractive for communication systems with their large variety of existing and emerging standards due to their flexibil...
Frank Gilbert, Michael J. Thul, Norbert Wehn
165
Voted
IPPS
2003
IEEE
15 years 9 months ago
Dual Priority Algorithm to Schedule Real-Time Tasks in a Shared Memory Multiprocessor
In this paper we present an adaptation of the Dual Priority Scheduling Algorithm to schedule both hard realtime periodic tasks and soft-aperiodic tasks in shared memory multiproce...
Josep M. Banús, Alex Arenas, Jesús L...
132
Voted
ASAP
2000
IEEE
142views Hardware» more  ASAP 2000»
15 years 8 months ago
Contention-Conscious Transaction Ordering in Embedded Multiprocessors
This paper explores the problem of efficiently ordering interprocessor communication operations in statically-scheduled multiprocessors for iterative dataflow graphs. In most digi...
Mukul Khandelia, Shuvra S. Bhattacharyya
100
Voted
ICCD
2000
IEEE
69views Hardware» more  ICCD 2000»
15 years 8 months ago
Hierarchical Simulation of a Multiprocessor Architecture
When proposing new architectural enhancements, it is also important to account for the hardware complexity. To achieve this goal, we propose to model the new design in a hardware ...
Marius Pirvu, Laxmi N. Bhuyan, Rabi N. Mahapatra
123
Voted
ICPPW
1999
IEEE
15 years 8 months ago
Multistage Ring Network: A New Multiple Ring Network for Large Scale Multiprocessors
We present a new multiple ring network for multiprocessors, called the Multistage Ring Network(MRN). The MRN has a 2-level hierarchy of register insertion rings, and its interconn...
Dongho Yoo, Inbum Jung, Seung Ryoul Maeng, Hyungla...