Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors

Software implementations of channel decoding algorithms are attractive for communication systems with their large variety of existing and emerging standards due to their flexibility and extensibility. For high throughput, however, a single processor can not provide the necessary compute power. Using several processors in parallel without exploiting the internal parallelism of the algorithm leads to intolerable overhead in area, power consumption, and latency. We propose a multiprocessor based Turbo-Decoder implementation where inherently parallel decoding tasks are mapped onto individual processing nodes. The implied challenging inter-processor communication is efficiently handled by our framework such that throughput is not degraded. In this paper we present communication centric architectures from buses to heterogenous networks that allow to interconnect numerous processors to perform high throughput Turbo-decoding.

• Type: Conference
• Year: 2003
• Where: DATE
• Authors: Frank Gilbert, Michael J. Thul, Norbert Wehn
• Keywords: Channel Decoding Algorithms, DATE 2003, Hardware, Necessary Compute Power, Parallel Decoding Tasks