177 search results - page 24 / 36 » A Single-Path Chip-Multiprocessor System |
ISCA
2008
IEEE
14 years 1 months ago
2008
IEEE
Efficiently utilizing off-chip DRAM bandwidth is a critical issue in designing cost-effective, high-performance chip multiprocessors (CMPs). Conventional memory controllers deli...
MICRO
2007
IEEE
14 years 1 months ago
2007
IEEE
Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processo...
MICRO
2007
IEEE
14 years 1 months ago
2007
IEEE
In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses...
NOCS
2007
IEEE
14 years 1 months ago
2007
IEEE
Recent remarkable advances in nanoscale siliconphotonic integrated circuitry specifically compatible with CMOS fabrication have generated new opportunities for leveraging the uni...
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
Networks-on-Chip (NoCs) have been recently proposed as a promising solution to complex on-chip communication problems. The lack of an unified representation of applications and ar...