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FPGA
1999
ACM
174views FPGA» more  FPGA 1999»
13 years 12 months ago
Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs
Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimized towards specific applications...
Peter Kollig, Bashir M. Al-Hashimi
TACO
2008
130views more  TACO 2008»
13 years 7 months ago
Efficient hardware code generation for FPGAs
r acceptance of FPGAs as a computing device requires a higher level of programming abstraction. ROCCC is an optimizing C to HDL compiler. We describe the code generation approach i...
Zhi Guo, Walid A. Najjar, Betul Buyukkurt
DAC
2004
ACM
14 years 8 months ago
FPGA power reduction using configurable dual-Vdd
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
Fei Li, Yan Lin, Lei He
ISCAS
2003
IEEE
135views Hardware» more  ISCAS 2003»
14 years 29 days ago
Formal verification of LTL formulas for SystemC designs
To handle today’s complexity, modern circuits and systems be specified at a high level of abstraction. Recently, SystemC has been proposed as a language that allows a fast on o...
Daniel Große, Rolf Drechsler
ECOOP
2008
Springer
13 years 9 months ago
Liquid Metal: Object-Oriented Programming Across the Hardware/Software Boundary
Abstract. The paradigm shift in processor design from monolithic processors to multicore has renewed interest in programming models that facilitate parallelism. While multicores ar...
Shan Shan Huang, Amir Hormati, David F. Bacon, Rod...