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» A Study on Impact of Leakage Current on Dynamic Power
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ASPDAC
2004
ACM
126views Hardware» more  ASPDAC 2004»
14 years 29 days ago
High-level area and power-up current estimation considering rich cell library
— Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces la...
Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel,...
EUC
2008
Springer
13 years 9 months ago
Dynamic and Leakage Power Minimization with Loop Voltage Scheduling and Assignment
This paper studies the scheduling and assignment problem that minimizes the total energy including both dynamic and leakage energy for applications with loops on multi-voltage, mul...
Meikang Qiu, Jiande Wu, Jingtong Hu, Yi He, Edwin ...
PACS
2000
Springer
121views Hardware» more  PACS 2000»
13 years 11 months ago
Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power
Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadvertently will lead to an exponential increase in leakage power dissipation. In this work we ex...
Stefanos Kaxiras, Zhigang Hu, Girija J. Narlikar, ...
ICCAD
2002
IEEE
157views Hardware» more  ICCAD 2002»
14 years 4 months ago
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads
Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak performance is unnecessary. However, the achievable power savings by DVS alone is becoming limi...
Steven M. Martin, Krisztián Flautner, Trevo...
CF
2005
ACM
13 years 9 months ago
Controlling leakage power with the replacement policy in slumberous caches
As technology scales down at an exponential rate, leakage power is fast becoming the dominant component of the total power budget. A large share of the total leakage power is diss...
Nasir Mohyuddin, Rashed Bhatti, Michel Dubois