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VLSID
1996
IEEE
133views VLSI» more  VLSID 1996»
14 years 13 hour ago
Allocation and Binding in Data Path Synthesis Using a Genetic Algorithm Approach
A technique for allocatzon and binding for data path synthesis (DPS) using a Genetic Algorithm (GA) approach has been developed. The proposed genetic algorithm uses a non-conventi...
Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy G...
ISQED
2006
IEEE
78views Hardware» more  ISQED 2006»
14 years 1 months ago
Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines
Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. This paper develops closed-form models to predict the dela...
Andrew Havlir, David Z. Pan
DAC
2008
ACM
13 years 9 months ago
Topology synthesis of analog circuits based on adaptively generated building blocks
This paper presents an automated analog synthesis tool for topology generation and subsequent circuit sizing. Though sizing is indispensable, the paper mainly concentrates on topo...
Angan Das, Ranga Vemuri
ISCAS
2006
IEEE
119views Hardware» more  ISCAS 2006»
14 years 1 months ago
Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis
In this paper we present two polynomial time-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis through simulta...
Saraju P. Mohanty, Elias Kougianos, Ramakrishna Ve...
DAC
2008
ACM
14 years 8 months ago
Enhancing timing-driven FPGA placement for pipelined netlists
FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
Kenneth Eguro, Scott Hauck