System-on-Chip (SoC) design methodologies rely heavily on reuse of intellectual property (IP) blocks. IP reuse is a labour intensive and time consuming process as IP blocks often ...
High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test patte...
We present a computer-aided design flow for quantum circuits, complete with automatic layout and control logic extraction. To motivate automated layout for quantum circuits, we in...
Mark Whitney, Nemanja Isailovic, Yatish Patel, Joh...
Stalls, due to mis-matches in communication rates, are a major performance obstacle in pipelined circuits. If the rate of data production is faster than the rate of consumption, t...
Microfluidic biochips are revolutionizing many areas of biochemistry and biomedical sciences. Several synthesis tools have recently been proposed for the automated design of bioch...