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ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
14 years 1 months ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan
DAC
2005
ACM
14 years 8 months ago
Operator-based model-order reduction of linear periodically time-varying systems
eriodically time-varying (LPTV) abstractions are useful for a variety of communication and computer subsystems. In this paper, we present a novel operator-based model-order reduct...
Yayun Wan, Jaijeet S. Roychowdhury
EVOW
2001
Springer
14 years 9 days ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...
DAC
2005
ACM
13 years 9 months ago
Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips
Microfluidic biochips promise to revolutionize biosensing and clinical diagnostics. As more bioassays are executed concurrently on a biochip, system integration and design complex...
Fei Su, Krishnendu Chakrabarty
GECCO
2003
Springer
120views Optimization» more  GECCO 2003»
14 years 1 months ago
Multi-FPGA Systems Synthesis by Means of Evolutionary Computation
Abstract. Multi-FPGA systems (MFS) are used for a great variety of applications, for instance, dynamically re-configurable hardware applications, digital circuit emulation, and num...
José Ignacio Hidalgo, Francisco Ferná...