284 search results - page 41 / 57 » A Synthesis Algorithm for Modular Design of Pipelined Circui... |
GLVLSI
2011
IEEE
12 years 11 months ago
2011
IEEE
Existing optimization algorithms for the multiplierless realization of multiple constant multiplications (MCM) typically target the minimization of the number of addition and subt...
ICIAP
2003
ACM
14 years 8 months ago
2003
ACM
This paper presents Olympus, a modular processing architecture for a distributed ambient intelligence. The system is aimed at detailed reporting of people wandering and gesturing ...
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
The synthesis of clock network in the presence of process variation is becoming a vital design issue towards the performance of digital circuits. In this paper, we propose a clock ...
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Volta...
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
—A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of Functional Units has a great i...