284 search results - page 49 / 57 » A Synthesis Algorithm for Modular Design of Pipelined Circui... |
CODES
2008
IEEE
14 years 2 months ago
2008
IEEE
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
DAC
2000
ACM
14 years 8 months ago
2000
ACM
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
IH
2004
Springer
14 years 1 months ago
2004
Springer
In this paper, we consider how to hide information into finite state machine (FSM), one of the popular computation models. The key advantage of hiding information in FSM is that t...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
In a behavioral synthesis system, a typical approach used to guide the scheduler is to impose hard constraints on the relative timing between operations considering performance, a...