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ICCAD
2007
IEEE
102views Hardware» more  ICCAD 2007»
14 years 4 months ago
Scalable exploration of functional dependency by interpolation and incremental SAT solving
Functional dependency is concerned with rewriting a Boolean function f as a function h over a set of base functions {g1, …, gn}, i.e. f = h(g1, …, gn). It plays an important r...
Chih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang H...
ISPD
2010
ACM
195views Hardware» more  ISPD 2010»
14 years 2 months ago
Density gradient minimization with coupling-constrained dummy fill for CMP control
In the nanometer IC design, dummy fill is often performed to improve layout pattern uniformity and the post-CMP quality. However, filling dummies might greatly increase intercon...
Huang-Yu Chen, Szu-Jui Chou, Yao-Wen Chang
ISQED
2010
IEEE
227views Hardware» more  ISQED 2010»
14 years 2 months ago
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, ...
ISPD
2004
ACM
134views Hardware» more  ISPD 2004»
14 years 1 months ago
Performance-driven register insertion in placement
As the CMOS technology is scaled into the dimension of nanometer, the clock frequencies and die sizes of ICs are shown to be increasing steadily [5]. Today, global wires that requ...
Dennis K. Y. Tong, Evangeline F. Y. Young
ISPD
2010
ACM
217views Hardware» more  ISPD 2010»
14 years 2 months ago
ITOP: integrating timing optimization within placement
Timing-driven placement is a critical step in nanometerscale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a c...
Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy,...