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ICPP
2002
IEEE
14 years 1 months ago
Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications
Code size expansion of software-pipelined loops is a critical problem for DSP systems with strict code size constraint. Some ad-hoc code size reduction techniques were used to try...
Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha
ETFA
2008
IEEE
13 years 10 months ago
Feasibility analysis for networked control systems by simulation in Modelica
Technological advancements in communication and embedded computing lead to the increasing application of decentralized structures in automation and control. The decentralization a...
Liu Liu, Georg Frey
MICRO
2000
IEEE
176views Hardware» more  MICRO 2000»
13 years 8 months ago
An Advanced Optimizer for the IA-64 Architecture
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel M....
DATE
2004
IEEE
210views Hardware» more  DATE 2004»
14 years 9 days ago
Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow
Emerging embedded system applications in multimedia and image processing are characterized by complex control flow consisting of deeply nested conditionals and loops. We present a...
Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alexandru N...
ISSS
2002
IEEE
151views Hardware» more  ISSS 2002»
14 years 1 months ago
Tuning of Loop Cache Architectures to Programs in Embedded System Design
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
Frank Vahid, Susan Cotterell