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» A System Level Resource Estimation Tool for FPGAs
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DATE
2007
IEEE
109views Hardware» more  DATE 2007»
14 years 5 months ago
System level clock tree synthesis for power optimization
The clock tree is the interconnect net on Systems-on-Chip (SoCs) with the heaviest load and consumes up to 40% of the overall power budget. Substantial savings of the overall powe...
Saif Ali Butt, Stefan Schmermbeck, Jurij Rosenthal...
HICSS
2008
IEEE
161views Biometrics» more  HICSS 2008»
14 years 5 months ago
IT Business Alignment as Governance Tool for Firm-Internal Relationship Quality: A Longitudinal Case Study
Many business processes are relying on a smooth and flexible IT support. A major finding of IS research is that in order to generate value from IT the complementarities between IT...
Heinz-Theo Wagner, Tim Weitzel
DATE
2010
IEEE
121views Hardware» more  DATE 2010»
14 years 3 months ago
Cost modeling and cycle-accurate co-simulation of heterogeneous multiprocessor systems
—In this paper, we present a method to analyze different implementations of stream-based applications on heterogeneous multiprocessor systems. We take both resource usage and per...
Sven van Haastregt, Eyal Halm, Bart Kienhuis
HPCC
2007
Springer
14 years 2 months ago
Resource Aggregation and Workflow with Webcom
Efficient exploitation of the aggregate resources available to a researcher is a challenging and real problem. The challenge becomes all the greater when researchers who collaborat...
Oisín Curran, Paddy Downes, John Cunniffe, ...
ASPDAC
2004
ACM
89views Hardware» more  ASPDAC 2004»
14 years 2 months ago
Predictable design of low power systems by pre-implementation estimation and optimization
- Each year tens of billions of Dollars are wasted by the microelectronics industry because of missed deadlines and delayed design projects. These delays are partially due to desig...
Wolfgang Nebel