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» A Systematic Approach for Designing Testable VLSI Circuits
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GLVLSI
1999
IEEE
88views VLSI» more  GLVLSI 1999»
14 years 1 days ago
Logic in Wire: Using Quantum Dots to Implement a Microprocessor
Despite the seemingly endless upwards spiral of modern VLSI technology, many experts are predicting a hard wall for CMOS in about a decade. Given this, researchers continue to loo...
Michael T. Niemier, Peter M. Kogge
VTS
1999
IEEE
106views Hardware» more  VTS 1999»
14 years 7 hour ago
RT-level TPG Exploiting High-Level Synthesis Information
High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test patte...
Silvia Chiusano, Fulvio Corno, Paolo Prinetto
ISLPED
2007
ACM
97views Hardware» more  ISLPED 2007»
13 years 9 months ago
Detailed placement for leakage reduction using systematic through-pitch variation
We present a novel detailed placement technique that accounts for systematic through-pitch variations to reduce leakage. Leakage depends nearly exponentially on linewidth (gate le...
Andrew B. Kahng, Swamy Muddu, Puneet Sharma
IJCV
1998
81views more  IJCV 1998»
13 years 7 months ago
Estimating the Focus of Expansion in Analog VLSI
In the course of designing an integrated system for locating the focus of expansion (FOE) from a sequence of images taken while a camera is translating, a variety of direct motion ...
Ignacio S. McQuirk, Berthold K. P. Horn, Hae-Seung...
VLSID
2002
IEEE
159views VLSI» more  VLSID 2002»
14 years 8 months ago
Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon
Increasing complexity of the functionalities and the resultant growth in number of gates integrated in a chip coupled with shrinking geometries and short cycle time requirements br...
Karanth Shankaranarayana, Soujanna Sarkar, R. Venk...