209 search results - page 3 / 42 » A Systematic Approach for Designing Testable VLSI Circuits |
DFT
2002
IEEE
14 years 20 days ago
2002
IEEE
Concurrent error detection (CED) methods are typically employed to provide an indication of the operational health of synchronous circuits during normal functionality. Existing CE...
CCS
2009
ACM
13 years 11 months ago
2009
ACM
We present an approach for the design and analysis of an electronic voting machine based on a novel combination of formal verification and systematic testing. The system was desig...
DAC
2009
ACM
14 years 2 months ago
2009
ACM
For a computing system to be trusted, it is equally important to verify that the system performs no more and no less functionalities than desired. Traditional testing and verifica...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
A stochastic global optimization approach is presented for transistor sizing in CMOS VLSI circuits. This is a direct search strategy for the best design among feasible ones, with ...
EH
2003
IEEE
14 years 1 months ago
2003
IEEE
The paper deals with a class of image filters in which the evolutionary approach consistently produces excellent and innovative results. Furthermore, a method is proposed that le...