36 search results - page 7 / 8 » A Systematic Approach for Diagnosing Multiple Delay Faults |
ITC
2002
IEEE
14 years 16 days ago
2002
IEEE
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
ICSM
2006
IEEE
14 years 1 months ago
2006
IEEE
The test case execution order affects the time at which the objectives of testing are met. If the objective is fault detection, an inappropriate execution order might reveal most ...
DDECS
2007
IEEE
14 years 1 months ago
2007
IEEE
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...
IROS
2007
IEEE
14 years 1 months ago
2007
IEEE
— Any system that has the capability to diagnose and recover from faults is considered to be a fault-tolerant system. Additionally, the quality of the incorporated fault-toleranc...
ASAP
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper we introduce a design methodology that allows the system/circuit designer to build reliable systems out of unreliable nano-scale components. The central point of our...