106 search results - page 13 / 22 » A Task-Centric Memory Model for Scalable Accelerator Archite... |
CF
2010
ACM
14 years 29 days ago
2010
ACM
Over the past decade, the trajectory to the petascale has been built on increased complexity and scale of the underlying parallel architectures. Meanwhile, software developers hav...
OOPSLA
2010
Springer
13 years 6 months ago
2010
Springer
Heterogeneous multi-core processors, such as the IBM Cell processor, can deliver high performance. However, these processors are notoriously difficult to program: different cores...
ASPLOS
2011
ACM
12 years 11 months ago
2011
ACM
Providing deterministic execution significantly simplifies the debugging, testing, replication, and deployment of multithreaded programs. Recent work has developed deterministic...
CODES
2006
IEEE
13 years 9 months ago
2006
IEEE
The lack of memory safety in many popular programming languages, including C and C++, has been a cause for great concern in the realm of software reliability, verification, and mo...
EUROSYS
2007
ACM
14 years 5 months ago
2007
ACM
Software transactional memory (STM) is a promising technique for controlling concurrency in modern multi-processor architectures. STM aims to be more scalable than explicit coarse...