Sciweavers

819 search results - page 52 / 164
» A Technique for Combined Virtual Prototyping and Hardware De...
Sort
View
ICCAD
2006
IEEE
108views Hardware» more  ICCAD 2006»
14 years 5 months ago
Soft error reduction in combinational logic using gate resizing and flipflop selection
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
Rajeev R. Rao, David Blaauw, Dennis Sylvester
ASPLOS
2006
ACM
14 years 2 months ago
Geiger: monitoring the buffer cache in a virtual machine environment
Virtualization is increasingly being used to address server management and administration issues like flexible resource allocation, service isolation and workload migration. In a...
Stephen T. Jones, Andrea C. Arpaci-Dusseau, Remzi ...
SP
2002
IEEE
13 years 7 months ago
VLAM-G: A Grid-based virtual laboratory
The Grid-based Virtual Laboratory AMsterdam (VLAM-G), provides a science portal for distributed analysis in applied scientific research. It offers scientists experiment control, d...
Hamideh Afsarmanesh, Robert G. Belleman, Adam Bell...
ISQED
2008
IEEE
98views Hardware» more  ISQED 2008»
14 years 2 months ago
Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)
We proposed a combined magnetic and circuit level technique to explore the design methodology of SpinTorque Transfer RAM (SPRAM). A dynamic magnetic model of magnetic tunneling ju...
Yiran Chen, Xiaobin Wang, Hai Li, Harry Liu, Dimit...
MICRO
2008
IEEE
142views Hardware» more  MICRO 2008»
14 years 2 months ago
NBTI tolerant microarchitecture design in the presence of process variation
—Negative bias temperature instability (NBTI), which reduces the lifetime of PMOS transistors, is becoming a growing reliability concern for sub-micrometer CMOS technologies. Par...
Xin Fu, Tao Li, José A. B. Fortes