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CASES
2010
ACM
13 years 6 months ago
Improved procedure placement for set associative caches
The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boos...
Yun Liang, Tulika Mitra
MICRO
2009
IEEE
129views Hardware» more  MICRO 2009»
14 years 3 months ago
Execution leases: a hardware-supported mechanism for enforcing strong non-interference
High assurance systems such as those found in aircraft controls and the financial industry are often required to handle a mix of tasks where some are niceties (such as the contro...
Mohit Tiwari, Xun Li, Hassan M. G. Wassel, Frederi...
LREC
2010
236views Education» more  LREC 2010»
13 years 10 months ago
ProPOSEC: A Prosody and PoS Annotated Spoken English Corpus
We have previously reported on ProPOSEL, a purpose-built Prosody and PoS English Lexicon compatible with the Python Natural Language ToolKit. ProPOSEC is a new corpus research res...
Claire Brierley, Eric Atwell
ISSAC
2007
Springer
177views Mathematics» more  ISSAC 2007»
14 years 2 months ago
Component-level parallelization of triangular decompositions
We discuss the parallelization of algorithms for solving polynomial systems symbolically by way of triangular decompositions. We introduce a component-level parallelism for which ...
Marc Moreno Maza, Yuzhen Xie
LCTRTS
2007
Springer
14 years 2 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...