264 search results - page 11 / 53 » A Time Predictable Instruction Cache for a Java Processor |
RTSS
2006
IEEE
14 years 2 months ago
2006
IEEE
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
ICS
1999
Tsinghua U.
14 years 29 days ago
1999
Tsinghua U.
—This paper explores the use of compiler optimizations which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying ...
VLDB
2004
ACM
14 years 2 months ago
2004
ACM
Online transaction processing (OLTP) is a multibillion dollar industry with high-end database servers employing state-of-the-art processors to maximize performance. Unfortunately,...
DATE
2008
IEEE
14 years 3 months ago
2008
IEEE
Efficient use of the memory hierarchy is critical for achieving high performance in a multiprocessor systemon-chip. An external memory that is shared between processors is a bottl...
MICRO
1999
IEEE
14 years 29 days ago
1999
IEEE
This paper studies an interesting yet less explored behavior of memory access instructions, called access region locality. Unlike the traditional temporal and spatial data localit...