264 search results - page 14 / 53 » A Time Predictable Instruction Cache for a Java Processor |
ATVA
2004
Springer
14 years 2 months ago
2004
Springer
nded Abstract – Oleg Parshin∗ Abdur Rakib† Stephan Thesing∗ Reinhard Wilhelm∗ The precise determination of worst-case execution times (WCETs) for programs is mostly bein...
DAC
2007
ACM
14 years 9 months ago
2007
ACM
Static worst-case execution time (WCET) analysis is done by modeling the hardware behavior. In this paper we describe a WCET analysis technique to analyze systems with function ca...
RTAS
2008
IEEE
14 years 3 months ago
2008
IEEE
Recent technologies such as the Real-Time Specification for Java promise to bring Java’s advantages to real-time systems. While these technologies have made Java more predictab...
HPCA
2006
IEEE
14 years 9 months ago
2006
IEEE
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...
IEEEPACT
2006
IEEE
14 years 2 months ago
2006
IEEE
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...