264 search results - page 17 / 53 » A Time Predictable Instruction Cache for a Java Processor |
104
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ICPP
2005
IEEE
15 years 7 months ago
2005
IEEE
Java-based middleware is a rapidly growing workload for high-end server processors, particularly Chip Multiprocessors (CMP). To help architects design future microprocessors to ru...
113
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PDPTA
2003
15 years 3 months ago
2003
The performance of the data memory hierarchy is extremely important in current and near future high performance superscalar microprocessors. To address the memory gap, computer de...
101
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HPCA
2009
IEEE
16 years 2 months ago
2009
IEEE
Some instructions have more impact on processor performance than others. Identification of these critical instructions can be used to modify and improve instruction processing. Pr...
124
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ARCS
2006
Springer
15 years 6 months ago
2006
Springer
While trace cache, value prediction, and prefetching have been shown to be effective in the single-threaded superscalar, there has been no analysis of these techniques in a Simulta...
121
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ISCA
2000
IEEE
15 years 6 months ago
2000
IEEE
Trace caches enable high bandwidth, low latency instruction supply, but have a high miss penalty and relatively large working sets. Consequently, their performance may suffer due ...