264 search results - page 21 / 53 » A Time Predictable Instruction Cache for a Java Processor |
HPCA
2004
IEEE
14 years 9 months ago
2004
IEEE
Modern out-of-order processors tolerate long latency memory operations by supporting a large number of inflight instructions. This is particularly useful in numerical applications...
ISCA
1998
IEEE
14 years 28 days ago
1998
IEEE
For maximum performance, an out-of-order processor must issue load instructions as early as possible, while avoiding memory-order violations with prior store instructions that wri...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
We introduce a new non-intrusive on-chip cache-tuning hardware module capable of accurately predicting the best configuration of a configurable cache for an executing application....
CASES
2008
ACM
13 years 10 months ago
2008
ACM
Performance evaluation of embedded software is essential in an early development phase so as to ensure that the software will run on the embedded device's limited computing r...
IEEEPACT
2002
IEEE
14 years 1 months ago
2002
IEEE
Memory dependence prediction allows out-of-order issue processors to achieve high degrees of instruction level parallelism by issuing load instructions at the earliest time withou...