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» A Time Predictable Instruction Cache for a Java Processor
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ISCA
2003
IEEE
88views Hardware» more  ISCA 2003»
14 years 1 months ago
Phase Tracking and Prediction
In a single second a modern processor can execute billions of instructions. Obtaining a bird’s eye view of the behavior of a program at these speeds can be a difficult task whe...
Timothy Sherwood, Suleyman Sair, Brad Calder
CASCON
1996
118views Education» more  CASCON 1996»
13 years 10 months ago
Automatic parallelization for symmetric shared-memory multiprocessors
The trend in workstation hardware is towards symmetric shared-memory multiprocessors (SMPs). User expectations are for (largely) automatic exploitation of parallelismon an SMP, si...
Jyh-Herng Chow, Leonard E. Lyon, Vivek Sarkar
EDCC
2006
Springer
14 years 8 days ago
SEU Mitigation Techniques for Microprocessor Control Logic
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
T. S. Ganesh, Viswanathan Subramanian, Arun K. Som...
ICS
1998
Tsinghua U.
14 years 25 days ago
Load Execution Latency Reduction
In order to achieve high performance, contemporary microprocessors must effectively process the four major instruction types: ALU, branch, load, and store instructions. This paper...
Bryan Black, Brian Mueller, Stephanie Postal, Ryan...
MICRO
2009
IEEE
178views Hardware» more  MICRO 2009»
14 years 3 months ago
Improving cache lifetime reliability at ultra-low voltages
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption. However, the increased severity of manufacturing-induced parameter variations a...
Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerso...